Why do people use timing derates at 90 nm and below as opposed to using clock uncertainty?

The purpose for timing derates and clock uncertainty is to over constraint the design. At higher tech nodes (like 0.18 um and above), people used to rely on clock uncertainty to make sure they hit the required frequency target for the chip. But, at 90nm and below, people use timing derates and/or clock uncertainty to over constraint the design.

The reason behind using timing derates at lower geometries is to allow taking OCV related effects and more path specific effects into account. For example, assume that you have a path which is 5-stages long and other paths which is 40-stages long. With help of clock uncertainty you are going to penalize both the paths by same amount thus overcontraining your design. With help of timing derates you are allocating budgets according to the path length and nature. This will do less overconstraining on your design and thus get you more silicon area :)