Which Clock tree is better?

There are two clock trees build for the same 65nm-block: One with 1.2ns latency and 150ps skew and other has 2ns latency and 100ps skew. Which clock tree is better and why?

Answer is clock tree with 1.2ns latency and 150 ps is better.
Why?
At 65nm, the timing derates and OCV effects will come into play. Clock trees with longer latency are more susceptible to all this. Also, CRPR claiming needed on a 1.2ns clock tree is much less than 2.0ns clock tree. If the branching has not happened at the very end, you cannot claim a lot of CRPR on the 2.0ns clock tree and it will in-turn cause lot of timing disturbance in the design. Of course, this is assuming that the design is using timing derates.

If design is not using timing derates, still due to OCV related effects, 1.2ns latency tree is favoured. In addition, most likely 2.0ns tree will be using more # of clock drivers and thus more clock tree power. Since the latency is large, it may be possible that the clock waveform can be sluggish if the clock transitions are not maintained properly. From the design practice, standpoint too, you dont want the clock latency to be too long else it becomes more un-predictable to deliver the clock efficiently to all parts of the chip.

But wait, what about skew? The clock tree with 2ns latency has 100ps skew. Ain't that good?
This skew is global skew. So, it may be between two branches which has no timing relationship. So, really claiming that we have a better skew may not mean anything since in reality the two flops which are really talking (from timing standpoint) may have much better skew and that is what we are really concerned about.

Why do people use timing derates at 90 nm and below as opposed to using clock uncertainty?

The purpose for timing derates and clock uncertainty is to over constraint the design. At higher tech nodes (like 0.18 um and above), people used to rely on clock uncertainty to make sure they hit the required frequency target for the chip. But, at 90nm and below, people use timing derates and/or clock uncertainty to over constraint the design.

The reason behind using timing derates at lower geometries is to allow taking OCV related effects and more path specific effects into account. For example, assume that you have a path which is 5-stages long and other paths which is 40-stages long. With help of clock uncertainty you are going to penalize both the paths by same amount thus overcontraining your design. With help of timing derates you are allocating budgets according to the path length and nature. This will do less overconstraining on your design and thus get you more silicon area :)

Why do people build clock tree with SVT cells and rest of the design with HVT cells?

There are several reason and advantages for doing this:

- SVT cells are faster as compared to HVT cells. So, you can get better clock latency by using SVT cells.
- Better latency can also result in less OCV effect (i.e. less CRPR to claim etc) and thus better timing.
- Numbers of clock buffers need to build the clock tree are less. This results in better dynamic power since the clock tree is always active and dynamic power is directly proportional to the number of cells used in the design. So, although you are going to have more leakage power, your overall chip power can still be substantially saved by this.
- You can also save area by using less number of clock buffers. Useful if you have a complex clock tree and design is already congested after place_opt.
- HVT cells are more prone to SI/noise effects. Using SVT cells, you can guarantee that there will be minimal SI effects on the clock network.

HVT = High Vth threshold
SVT = Standard Vth threshold
LVT = Low Vth threshold

Why this blog?

Most of my time is spent interacting with physical designers. Sometimes I also interview potential AE candidates. What I have seen is that lot of people know common physical design terms but don't really know the details beneath it or what are the potential implications/advantages of one over the other.

With economy in dire state, there are lot of people looking out for job or trying to improve their skills. But, they are left with very little choice to learn new things or explore in-depth into why things have to be done in certain way.

I have been in the physical implementation field since past 10 years and is working with lot of customers and that puts me in a unique position to understand some of these things and share the same with readers. Lot of these may be really fundamental and in some cases you may even know what I am talking about but, I am sure there will be some people who can find value or learn something from it.

I will try to come up with some topics every week and try to post at least once a week. Please post your comments so that I can do necessary variation to my future posts...

And last not the least, the views expressed here are all my own and is not endorsed or no way representative of the company I work with or used to work with :)