Why do people build clock tree with SVT cells and rest of the design with HVT cells?

There are several reason and advantages for doing this:

- SVT cells are faster as compared to HVT cells. So, you can get better clock latency by using SVT cells.
- Better latency can also result in less OCV effect (i.e. less CRPR to claim etc) and thus better timing.
- Numbers of clock buffers need to build the clock tree are less. This results in better dynamic power since the clock tree is always active and dynamic power is directly proportional to the number of cells used in the design. So, although you are going to have more leakage power, your overall chip power can still be substantially saved by this.
- You can also save area by using less number of clock buffers. Useful if you have a complex clock tree and design is already congested after place_opt.
- HVT cells are more prone to SI/noise effects. Using SVT cells, you can guarantee that there will be minimal SI effects on the clock network.

HVT = High Vth threshold
SVT = Standard Vth threshold
LVT = Low Vth threshold