Hold Fixing

At 65 and 40nm, hold fixing is becoming equally important as setup fixing. But, most of the P&R tools wont spent the same amount of effort in fixing hold violations as they do in setup. Traditionally, by inserting delay cell the path which is violating hold gets resolved. Nothing really wrong with this approach, but if there are 50K or 100K hold violations, inserting that many or more delay cells is overkill in terms of area. There are some other ways to handle this.



Here are some other ways hold violations can be fixed so that adding too many cells can be avoided:

a. Area recovery : Often overlooked, but by doing area recovery, the setup slack (or positive slack) on the path can be reduced and thus can help reduce the number of hold violations.

b. Using more HVT cells : Doing leakage power optimization has it's benefit with hold fixing as well. Using more HVT cells will slow down the timing path and can help fix the hold violation.

c. CTS : Clock trees can be build such that there is not so much skew in the best case corner. Using multi-corner cts can easily help address this.

d. Useful skew : Clock-trees can be skewed to address hold.

f. Using driver and receiver sizing can also help fixing hold violations.

When NOT to have "shut-down" power domain?

There has been a lot of talk about low power these days and one of the techniques which is widely published and used is to create shut-down region also some times referred to as multi-supply design or MTCMOS based design. You can search the net to find 1000s of articles on why this is useful and possible advantages associated with it.

But, have you ever wondered when NOT to create shut-down power domain in your chip?

Here are possible dis-advantages in creating shut-down region in your design:

- If your circuit is such it there is very little possibility to put it to sleep.
- If the cycle time to wake-up the circuit is not an acceptable spec for the application in which it is being used.
- Most of the EDA tools want this shut-down power domain in a separate hierarchy module. While this is not difficult to do, but if you are inheriting your RTL which is already 90% pre-written based on previous chip, it make it challenging to re-group your hierarchy to meet this need.
- Moreover, even if you have a hierarchy (module) identified to be shut-down, but not every element in there can be shut-down can introduce addition design constraints such as adding retention flops or creating always-on islands for these elements.
- MTCMOS switches occupy a finite area in your chip. So, by adding them you are going to have a bigger die size. In addition, you'll have to add control circuit to shut-down and wake up these cells. This also means more cells and thus bigger die size.
- MTCMOS switches are leaky when in on-state. This will add to the leakage power of the design when in on-state. This becomes an issue when your leakage power specs are very tight.
- MTCMOS requires accurate analysis of rush-current and circuit transients due to sudden wake-up of shut-down regions. While this is doable, it is going to put extra burden on the back-end designer to come up with the right number of switch cells and robust power plan.
- Using shut-down regions will add extra steps in your chip design flow in terms to IR analysis, verification and implementation. If you have tight design schedule and this flow is not in-place it is a sure no-go. This also means adding new tools and licenses in your flow which may be another reason from business stand-point (Yeah, lot of you'll dis-agree to this but how many times you have used certain tool just because that was the only one available for you?)

Any more you can think of? Feel free to comment...