At 65 and 40nm, hold fixing is becoming equally important as setup fixing. But, most of the P&R tools wont spent the same amount of effort in fixing hold violations as they do in setup. Traditionally, by inserting delay cell the path which is violating hold gets resolved. Nothing really wrong with this approach, but if there are 50K or 100K hold violations, inserting that many or more delay cells is overkill in terms of area. There are some other ways to handle this.
Here are some other ways hold violations can be fixed so that adding too many cells can be avoided:
a. Area recovery : Often overlooked, but by doing area recovery, the setup slack (or positive slack) on the path can be reduced and thus can help reduce the number of hold violations.
b. Using more HVT cells : Doing leakage power optimization has it's benefit with hold fixing as well. Using more HVT cells will slow down the timing path and can help fix the hold violation.
c. CTS : Clock trees can be build such that there is not so much skew in the best case corner. Using multi-corner cts can easily help address this.
d. Useful skew : Clock-trees can be skewed to address hold.
f. Using driver and receiver sizing can also help fixing hold violations.
Hi, Andy again. The number of hold violation is of course dependent on what PVT one uses. Typically it seems fast corner is at 0-degree. Is there any reason to use -25 or -40 in characterizing fast corner? Thanks.
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ReplyDeleteEven Inserting Hold Buffer's is not straight forward , we need to find convergence and divergence points before inserting the buffer . Most of the Tools don't fix few hold paths as the path doesn't have positive setup margin
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