Which Clock tree is better?

There are two clock trees build for the same 65nm-block: One with 1.2ns latency and 150ps skew and other has 2ns latency and 100ps skew. Which clock tree is better and why?

Answer is clock tree with 1.2ns latency and 150 ps is better.
Why?
At 65nm, the timing derates and OCV effects will come into play. Clock trees with longer latency are more susceptible to all this. Also, CRPR claiming needed on a 1.2ns clock tree is much less than 2.0ns clock tree. If the branching has not happened at the very end, you cannot claim a lot of CRPR on the 2.0ns clock tree and it will in-turn cause lot of timing disturbance in the design. Of course, this is assuming that the design is using timing derates.

If design is not using timing derates, still due to OCV related effects, 1.2ns latency tree is favoured. In addition, most likely 2.0ns tree will be using more # of clock drivers and thus more clock tree power. Since the latency is large, it may be possible that the clock waveform can be sluggish if the clock transitions are not maintained properly. From the design practice, standpoint too, you dont want the clock latency to be too long else it becomes more un-predictable to deliver the clock efficiently to all parts of the chip.

But wait, what about skew? The clock tree with 2ns latency has 100ps skew. Ain't that good?
This skew is global skew. So, it may be between two branches which has no timing relationship. So, really claiming that we have a better skew may not mean anything since in reality the two flops which are really talking (from timing standpoint) may have much better skew and that is what we are really concerned about.